Conventional semiconductor non-volatile memories, such as read-only memories (ROMs), erasable-programmable ROMs (EPROMs), electrically erasable-programmable ROMs (EEPROMs), and flash EEPROMs are typically constructed using a double-poly structure. Referring now to FIG. 1, there is shown a cross-sectional view of the cell structure of a conventional nonvolatile memory device 100 including a substrate 102 of a semiconductor crystal such as silicon. The device 100 also includes a channel region 104, a source region 106, a drain region 108, a floating gate dielectric layer 110, a floating poly gate electrode 112, an inter-gate dielectric layer 114, and a control poly gate electrode 116. The floating gate dielectric layer 110 isolates the floating gate from the underlying substrate 102 while the inter-gate dielectric layer 114 isolates the control and floating gates. As shown in FIG. 1, the floating gate dielectric layer 110, the floating poly gate electrode 112, the inter-gate dielectric layer 114, and the control poly gate electrode 116 are all disposed on the surface of the substrate 102.
As semiconductor devices and integrated circuits are scaled down in size, demands for the efficient use of space have increased. Heretofore, conventional non-volatile devices have utilized a cell structure where the floating gate and control gate are formed on a top surface of the semiconductor substrate as shown in FIG. 1. However, this type of cell structure is limited to the degree to which the active devices can be made smaller in order to increase cell packing density and performance. Additionally, the stacked dual gate structure which is formed on the substrate surface is sensitive to the overlaps between the floating gate and the source and drain junctions.